Adders are key to many circuits, including microprocessor architectures. Adders perform critical operations including arithmetic functions (addition, subtraction, multiplication), comparison functions, and incrementing or decrementing functions. Adders are of interest as a bottleneck to further improvements in the performance of microprocessors and other general and specific purpose circuits.
Approximation has been recognized as providing an opportunity to increase performance or reduce power consumption through use of a simplified or inaccurate circuit in application contexts where strict requirements are relaxed. Approximate design enables a tradeoff of accuracy in computation versus performance and/or power. Various approximate arithmetic designs have been proposed that provide a fixed approximation to achieve a set performance. The approximation is designed at a level that provides an error rate that is an acceptable penalty. If error detection and correction is used, the penalty rate is set such that correction still results in a net speed/computation benefit.
Lu described a faster adder which has shorter carry chains and considers only the previous k bits of input in computing a carry bit. Lu, “Speeding Up Processing with Approximation Circuits”, IEEE Computer 37(3) (2004) pp. 67-73. Verma et al. describe a modification of Lu's adder in the form of a variable latency speculative adder (VLSA). Verma et al., “Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design” (Proc. 2008, pp. 1250-1255). The Verma et al. paper describes a modification of Lu's approximate fast adder that includes error detection and correction to Lu's design. This modification is a variable-latency adder that produces a correct result very fast with extremely high probability using an approximation. When an error is detected, a correction term must be applied and the correct result is produced after is a time delay. Shin et al. also propose a data path redesign technique for various adders which cuts the critical path in the carry chain. Shin et al., “A Re-Design Technique for Datapath Modules in Error Tolerant Applications” (Proc. Asian Test Symp., 2008, pp. 431-437). Zhu et al. propose an error-tolerant adders (ETA). ETAI is divided into an accurate part and an inaccurate part to achieve approximate results. Zhu et al., “Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing” (IEEE Trans. on VLSI Systems 18(8) (2010), pp. 1225-1229). ETAII cuts carry propagation to speed up the adder, and ETAIIM modifies ETAII by connecting carry chains in accurate MSB parts. Individually and collectively, these approximate adder designs produce almost-correct results at prescribed accuracy for a particular application, and obtain power reductions or performance improvements in return.
These prior techniques are therefore restricted or at least best-suited to particular application contexts. In contexts where the accuracy requirement can change dynamically, the previous methods' benefits from the accuracy tradeoff are reduced since the implementation must be targeted to the maximum accuracy requirement.